Variable delay charge coupled device

ABSTRACT

A various CCD delay element in which extra delay stages are provided. The extra stages are either held at a given potential to pass all signals therethrough and thus to not contribute to the gain or are connected to the clock signals to thereby increase the delay.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a delay element employing a chargecoupled device.

2. Background of the Invention

Delay elements using charge coupled devices (called a CCD delay elementherein) are often used in color signal processing circuits for colorvideo cameras.

In a color signal separation circuit for a signal carrier frequencyseparation system, for instance, red (R) and blue (B) signals areproduced in the following manner. A color signal produced one horizontalscanning period before is added to or subtracted form what is producedby a color pickup element. A CCD delay element is employed to delay thecolor signal output by the one horizontal scanning period so as toimplement the aforesaid processing.

FIG. 1 is a vertical sectional view showing the principal part of aconventional two-phase clock transfer type CCD delay element by way ofexample.

In FIG. 1, there is show a two-phase clock transfer type CCD delayelement. A unit cell A is constituted by pair of transfer gateelectrodes formed on the surface of a p⁻ -type silicon substrate 1 andby P⁺⁻ -type transfer barriers 2 formed beneath one of the transfer gateelectrodes. One unit cell A receiving a clock signal φ₁ and another unitcell receiving another clock signal φ₂ are wired so that they aredisposed alternately in the transfer direction. In addition, there areformed an input diode 3 and an output diode 4 composed of P⁺ regions.The input diode 3 is separated by input gates G₁ and G₂ from the inputterminal of a group of unit cells A disposed in the transfer direction.Correspondingly, the output diode 4 is separated by an output gate OTGfrom the output terminal of the unit cell group. The input diode 3 isconnected to an input terminal IN and the output diode 4 to an outputterminal OUT.

FIG. 2 is a waveform chart showing the two-phase clock signals φ₁ andφ₂, whereas FIG. 3 is a graphic illustration of potential profiles of apotential well produced by the two-phase clock signals φ₁ and φ₂ atthree points of time t₁, t₂ and t₃. When a signal being delayed issupplied to the input terminal IN while the input gates G₁ and G₂ andthe output gate OTG are held on, the potential well produced in eachunit cell is allowed to provide transfer operation across the outputterminal OUT as show in FIG. 3. An output signal is produced by theoutput terminal OUT after the lapse of the delay time determined by thenumber of series unit cells A disposed in the transfer direction and theperiods of the two-phase clock signals φ₁ and φ₂.

The period of a transfer clock signal must be changed to effect theadjustment of delay time because the number of unit cells A isunchangeable once they have been manufactured according to standardsemiconductor IC technology as far as the conventional CCD delayelements are concerned. In consideration of the accuracy required,however, it is difficult to the adjust delay time so minutely as toregulate the oscillation circuit for producing the transfer clocksignals.

SUMMARY OF THE INVENTION

An object of the present invention is to provide, in view of theaforesaid problems, a CCD delay element capable of facilitating theadjustment of delay time.

In order to technically accomplish the aforesaid object, the presentinvention is designed to provide at least one series connectedadditional unit cell for use as an adjusting stage in a proper positionwhere a group of unit cells are formed in the transfer direction. Thedelay time is lengthened by applying a transfer signal to the adjustingstage so as to make the adjusting stage perform transfer operation,whereas the transfer gate electrode of the adjusting stage is locked upat a given potential to provide a channel for use as the current path ofsignal charges unaffected by the transfer clock signal, i.e., withoutcausing the generation of delay time, to shorten the delay time, wherebyan increase and decrease in the delay time can be adjusted.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a vertical sectional view showing the principal part of aconventional CCD delay element.

FIGS. 2 and 3 are graphic illustrations of the operation of the CCDdelay element of FIG. 1 in terms of clock signals and surface potential.

FIG. 4 is a vertical sectional view showing the principal part of adelay element embodying the present invention.

FIG. 5 is a vertical section a view showing the principal part ofanother delay element embodying the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 4 is a vertical sectional view showing the principal part of adelay element embodying the present invention.

In FIG. 4, there is shown a two-phase clock transfer type CCD delayelement, wherein a unit cell is composed of a pair of transfer gateelectrodes formed on the surface of a P⁻ -type silicon substrate 5 andP⁺⁻ -type transfer barriers 6 formed beneath one of the transfer gateelectrodes. A predetermined number of series unit cells are disposed inthe transfer direction to form a delay stage x₁. One group of unit cellsreceive a clock signal φ₁ from a clock oscillator 12 and another groupof unit cells receive a clock signal φ₂. The two groups of unit cellsare wired so that they are disposed alternately in the transferdirection. Moreover, there are formed sufficient stages of unit cells toobtain a reference delay time Td₁.

In addition to the delay stage x₁, two series unit cells having aconfiguration similar to that of the unit cells of the delay stage x₁are formed and constitute an adjusting stage x₂.

An input diode 7 and an outptut diode 8, which are composed of a P⁺-type region, are formed at the ends of the delay stage x₁ and of theadjusting stage x₂. The input and output diodes 7 and 8 are separatedfrom the unit cells by input gate G and an output gate OTG,respectively. The diode 7 is connected to an input terminal IN and thediode 8 to an output terminal OUT.

The operation of the CCD delay element thus constructed willsubsequently be described. The two-phase clock signals φ₁ and φ₂ arewave signals shown in FIG. 2 and a surface potential profile produced ineach unit cell of the delay stage x₁ corresponds to what is shown inFIG. 3.

When it is unnecessary to adjust the delay time Td₁ set at the delaystage x₁, the transfer gate electrodes Ch₁ and Ch₂ of the unit cells ofthe adjusting stage x₂ are both locked up at a given potential by acontrol circuit 13 to provide conduction channels allowing the chargesto move from the unit cells of the final stages of the delay stage x₁ tothe output gate OTG at all times. When a signal being transferred isapplied to the input terminal IN while the input and output gates G andOTG are held on, an output signal is sent out of the output terminal OUTafter the lapse of the delay time Td₁ determined by the periods of thedelay stage x₁ and the two-phase clock signals φ₁ and φ₂.

When an adjustment is made to lengthen the delay time T_(d1) set by thedelay stage x₁, the transfer gate electrodes Ch₁ and Ch₂ of the unitcells of the adjusting stage x₂ are properly connected through thecontrol circuit 13 to the signal lines of the two-phase clock signals φ₁and φ₂ so as to behave like the unit cells of the delay stage x₁.

More specifically, the wiring is arranged so that the clock signal φ₁ isapplied to the transfer gate electrode Ch₁, whereas the transfer gateelectrode Ch₂ remains locked up at the given potential to provide achannel for use in simply moving the charges. Consequently, a time delayΔτ₁ caused by the clock signal φ₁ applied to the transfer gate electrodeCh₁ is obtained and the delay time can be lengthened up to Td1+Δτ₁.

On the other hand, the transfer gate electrode Ch₁ is locked up at thegiven potential to cause the formation of a channel for use in simplymoving the charges, whereas the wiring is arranged so that the clocksignal φ₁ is applied to the transfer gate electrode Ch₂, therebyobtaining a time delay Δτ₂ caused by the clock signal φ₁ applied to thetransfer gate electrode Ch₂. The delay time can thus be lengthened up toTd1+Δτ₂.

Moreover, provided wiring is arranged so that the clock signal φ₁ isapplied to the transfer gate electrode Ch₁ and the clock signal φ₂ isapplied to the transfer gate electrode Ch₂, the time delay Δτ₁ caused bythe unit cell to which the clock signal φ₁ is combined with the timedelay Δτ₃ caused by the unit cell to which the clock signal φ₁ isapplied. Thereby the delay time can be set at Td₁ +Δτ₁ +Δτ₃.

In this case, importance should be attached to the connection of thetransfer gate electrodes Ch₁ and Ch₂ to the particular signal lines ofthe two-phase clock signals φ₁ and φ₂ in such a manner that thearrangement of the unit cells of the adjusting stage x₂ to which thetwo-phase signals φ₁ and φ₂ are applied should be equal to that of theunit cells of the delay stage x₁.

Although a description has been given of this embodiment which onlyincreases the delay time, the wiring may be prearranged as a modifiedembodiment, for instance, so that the clock signal φ₁ is applied to thetransfer gate electrode Ch₁ of FIG. 3 to make available delay time T'd₁as a reference. Then, the transfer gate electrode Ch₁ may connected tothe given potential and separated from the signal line of the clocksignal φ₁ to this provide a channel for simply allowing charges to pass.An arrangement for shortening the delay time can thus become possible.

Although the adjusting stage x₂ is installed in the final stage on theoutput terminal OUT side in the embodiment of FIG. 4, moreover, thepresent invention is not limited to the aforesaid arrangement and theadjusting stage x₂ may be provided next to the input gate G or in themiddle of the delay stage x₁. It is not always required to provide onlyone adjusting stag x₂, which may be dispersedly formed in the midst ofthe delay stage x₁. In this case, however, the unit cells of the delayand adjusting stages, to which the two-phase clock signals φ₁ and φ₂ areapplied should be arranged alternately in the transfer direction.

FIG. 5 is a vertical sectional view of the principal part another CCDdelay element of a four-phase clock transfer type embodying the presentinvention.

With respect to the construction of such a delay element, four transfergate electrodes a₁, a₂, a₃ and a₄ as a group constitute a unit cell andare formed on a p⁻ -type silicon substrate 9. A plurality of such unitcells are disposed in series in the transfer direction to form a delaystage y₁ of use in producing a reference delay time Td₂. Clock signalsφ₁, φ₂, φ₃ and φ₄ are applied to the first, second, third and fourthtransfer gates a₁, a₂, a₃, a₄ of the unit cells, respectively.

In addition to the delay stage y₁, an adjusting stage y₂ consisting offour transfer gates φ_(A) -φ_(d) having the same configuration as theseof the unit cells of the delay stage y₁ is formed.

An input diode 10 and an output diode 11, which are composed of a p⁺⁻-type region, are formed at the ends of the delay stage y₁ and theadjusting stage y₂ with an intermediate input gate G and an intermediateoutput gate OTG. The diode 10 is connected to an input terminal IN andthe diode 11 to an output terminal OUT.

Since the operation of such a CCD delay element thus constructed bymeans of the four-phase clock signals φ₁ -φ₄ is conventionally wellknown, the description thereof will be omitted. Instead, the adjustmentof the delay time mainly embodying the present invention will bedescribed.

First, the transfer gate electrodes φ_(A) -φ_(d) of the adjusting stagey₂ are locked up at a given potential by a control circuit to providechannels allowing the charges to move across the delay stage y₁ and theoutput gate OTG. When a signal is applied to the input terminal IN whilethe input and output gates G and OTG are held on, an output signal issent out of the output terminal OUT after the lapse of the delay timeTd₂ determined by the delay stage y₁ and the four-phase clock signals φ₁-φ₄.

A time delay Δτ₄ due to the transfer operation of the adjusting stage y₂is obtained, provided wiring is arranged so that the control circuitapplies the clock signals φ₁ -φ₄ to the transfer gate electrodes φ_(A)-φ_(D) of the adjusting stage y₂ in the same order to the electrode a₁-a₄ of the unit cells of the delay stage y₁. The delay time can therebybe lengthened up to Td₂₊Δτ₄.

As in the case of the first embodiment of FIG. 4 the adjusting stage y₂in this embodiment may also be provided in any proper portion of thedelays stage y₁ and needless to say a plurality of unit cells may beinstalled in the adjusting stage y₂.

As set forth above, the delay time can be made adjustable withoutadjusting the period of the clock signal produced by the clockoscillator. The delay stage is formed to a preset reference delay time.The prearranged series adjusting stage has at least more than one unitcell having the same configuration as that of the unit cellsconstituting the delay stage.

If the aforesaid adjustment is made when characteristic tests arecarried out during the process of manufacture under the semiconductor ICtechnology, production cost and time are reduced because any otherprocess other than that of altering wiring pattern design can ultimatelybe dispensed with to obtain optimum delay time. Moreover, each transfergate electrode of the adjusting stage may be connected to a particularbonding pad on the integrated circuit of the CCD delay element tocontrol the adjusting stage from the outside rather than through acontrol circuit.

Further, the present invention is applicable to not only the two-andfour-phase clock transfer type CCD delay elements but also three-phaseand other types of CCD delay elements by forming a unit cell having thesame configuration as that of each unit cell as for the adjusting stage.

In the CCD delay element thus constructed according to the presentinvention, at least more than one series additional unit cell for use asan adjusting stage is provided in a proper position where a group ofunit cells are formed in the transfer direction. The delay time islengthened by applying a transfer signal to the adjusting stage so as tomake the adjusting stage perform a time delaying transfer operation,whereas the transfer gate electrode of the adjusting stage is locked upat a given potential to provide a channel for use as the flow passage ofcharges to shorten the delay time, whereby an increase and decrease inthe delay time can readily be adjusted.

We claim:
 1. A CCD delay element, comprising:a delay stage of aplurality of charge-coupled-device unit cells arranged in a transferdirection; an adjusting stage of at least one charge-coupled-device unitcell of a same configuration as those of said delay stage and arrangedin series with said unit cells of said delay stage; clocking means forapplying clocking signals to said unit cells of said delay stage totransfer data signals along said transfer direction; and selective meansfor selectively applying at least one of said clocking signals and apredetermined locking potential to said unit cell of said adjustingstage, said locking potential applied to said unit cell of saidadjusting stage causing said unit cell of said adjusting stage to be aconduction channel to transfer said data signals thereacross withoutdelay, said one of said clocking signals applied to said unit cell ofsaid adjusting stage to transfer said data signals thereacross with adelay determined by a period of said clocking signals, whereby said datasignals are transferred across said delay stage and said adjusting stagewith a selective delay.
 2. A CCD delay element as recited in claim 1,wherein said selective means is an electronic circuit.
 3. A CCD delayelement as recited in claim 1, wherein said selective means includeslead wires connected to selected bonding pads of an integrated circuitincluding said delay stage, said adjusting stage and said clockingmeans.
 4. A CCD delay element as recited in claim 1, wherein saidadjusting stage includes at least two of said charge-coupled-device unitcells and said selective means selectively applies in any combinationsaid clocking signals and said locking potential to said at least twounit cells.